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AD829JN Fiches technique(PDF) 10 Page - Analog Devices

No de pièce AD829JN
Description  High Speed, Low Noise Video Op Amp
Download  16 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD829JN Fiches technique(HTML) 10 Page - Analog Devices

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REV. G
–10–
AD829
THEORY OF OPERATION
The AD829 is fabricated on Analog Devices’ proprietary comple-
mentary bipolar (CB) process, which provides PNP and NPN
transistors with similar fTs of 600 MHz. As shown in Figure 6,
the AD829 input stage consists of an NPN differential pair in
which each transistor operates at 600
µA collector current. This
gives the input devices a high transconductance, which in turn
gives the AD829 a low noise figure of 2 nV/
Hz @ 1 kHz.
The input stage drives a folded cascode that consists of a fast
pair of PNP transistors. These PNPs drive a current mirror that
provides a differential-input-to-single-ended-output conversion.
The high speed PNPs are also used in the current-amplifying
output stage, which provides high current gain of 40,000. Even
under conditions of heavy loading, the high fTs of the NPN and
PNPs, produced using the CB process, permits cascading two
stages of emitter followers while maintaining 60
° phase margin
at closed-loop bandwidths greater than 50 MHz.
Two stages of complementary emitter followers also effectively
buffer the high impedance compensation node (at the CCOMP pin)
from the output so the AD829 can maintain a high dc open-loop
gain, even into low load impedances: 92 dB into a 150
Ω load and
100 dB into a 1 k
Ω load. Laser trimming and PTAT biasing
ensure low offset voltage and low offset voltage drift, enabling
the user to eliminate ac coupling in many applications.
For added flexibility, the AD829 provides access to the internal
frequency compensation node. This allows the user to customize
frequency response characteristics for a particular application.
Unity gain stability requires a compensation capacitance of 68 pF
(Pin 5 to ground), which will yield a small signal bandwidth of
66 MHz and slew rate of 16 V/
µs. The slew rate and gain band-
width product will vary inversely with compensation capacitance.
Table I and Figure 8 show the optimum compensation capacitance
and the resulting slew rate for a desired noise gain. For gains
between 1 and 20, CCOMP can be chosen to keep the small signal
bandwidth relatively constant. The minimum gain that will still
provide stability depends on the value of external compensation
capacitance.
An RC network in the output stage (Figure 6) completely
removes the effect of capacitive loading when the amplifier is
compensated for closed-loop gains of 10 or higher. At low frequen-
cies, and with low capacitive loads, the gain from the compensation
node to the output is very close to unity. In this case, C is
bootstrapped and does not contribute to the compensation
capacitance of the device. As the capacitive load is increased, a
pole is formed with the output impedance of the output stage
this reduces the gain, and subsequently, C is incompletely boot-
strapped. Therefore, some fraction of C contributes to the
compensation capacitance, and the unity gain bandwidth falls. As
the load capacitance is further increased, the bandwidth continues
to fall and the amplifier remains stable.
Externally Compensating the AD829
The AD829 is stable with no external compensation for noise
gains greater than 20. For lower gains, two different methods of
frequency compensating the amplifier can be used to achieve
closed-loop stability: shunt and current feedback compensation.
IN
IN
+
1.2mA
OFFSET NULL
15
C
12.5pF
R
500
OUTPUT
+VS
–VS
CCOMP
15
Figure 6. Simplified Schematic
Shunt Compensation
Figures 7 and 8 show that shunt compensation has an external
compensation capacitor, CCOMP, connected between the com-
pensation pin and ground. This external capacitor is tied in
parallel with approximately 3 pF of internal capacitance at the
compensation node. In addition, a small capacitance, CLEAD,
in parallel with resistor R2, compensates for the capacitance at
the amplifier’s inverting input.
50
50
COAX
CABLE
–VS
0.1 F
CCOMP
0.1 F
AD829
CLEAD
R2
VOUT
R1
+VS
VIN
1k
Figure 7. Inverting Amplifier Connection Using External
Shunt Compensation
50
50
CABLE
–VS
0.1 F
CCOMP
0.1 F
AD829
VOUT
+VS
VIN
1k
R2
CLEAD
R1
Figure 8. Noninverting Amplifier Connection Using
External Shunt Compensation


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