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NBSG53AMNG Fiches technique(PDF) 3 Page - ON Semiconductor |
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NBSG53AMNG Fiches technique(HTML) 3 Page - ON Semiconductor |
3 / 18 page NBSG53A http://onsemi.com 3 Figure 3. Simplified Logic Diagram D D SEL CLK CLK VTD VCC Q Q Flip−Flop (DIV/2) Flip−Flop (DFF) R D D VTD OLS R Q Q VEE VTCLK VTCLK R 75 k W 75 k W 50 W 50 W 50 W 50 W 0 1 2 2 2 2 2 2 2 Table 2. OUTPUT LEVEL SELECT (OLS) OLS Q/Q VPP OLS Sensitivity VCC 800 mV OLS − 75 mV VCC − 0.4 V 200 mV OLS $ 150 mV VCC − 0.8 V 600 mV OLS $ 100 mV VCC − 1.2 V 0 OLS $ 75 mV VEE (Note 4) 400 mV OLS + 100 mV Float 600 mV N/A 4. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2.0 kW resistor should be connected from OLS to VEE. Table 3. TRUTH TABLE R SEL D CLK Q Function H x x x L Reset L H L Z L DFF L H H Z H DFF L L x Z Q DIV/2 Z = LOW to HIGH Transition Table 4. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTCLK, VTD and VTCLK, VTD to VCC LVDS Connect VTCLK, VTD and VTCLK, VTD Together AC−COUPLED Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (VIHCMR) RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal VTHR is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. This Voltage must be within the VTHR Specification. |
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Description similaire - NBSG53AMNG |
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