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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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WM8772 Fiches technique(PDF) 48 Page - Wolfson Microelectronics plc |
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WM8772 Fiches technique(HTML) 48 Page - Wolfson Microelectronics plc |
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48 / 73 page  WM8772EFT – 32 LEAD TQFP Production Data w PD Rev 4.2 October 2005 48 DEVICE DESCRIPTION INTRODUCTION WM8772EFT is a complete 6-channel DAC, 2-channel ADC audio codec, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi- bit sigma delta DACs with digital volume controls on each channel and output smoothing filters. The device is implemented as three separate stereo DACs and a stereo ADC in a single package and controlled by a single interface. Each stereo DAC has its own data input DIN1/2/3. DAC word clock DACLRC, DAC bit clock DACBCLK and DAC master clock DACMCLK are shared between them. The stereo ADC has it’s own data output DOUT, word clock ADCLRC, bit clock ADCBCLK and ADC master clock ADCMCLK. This allows the ADC and DAC to run independently. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode ADCLRC and ADCBCLK, DACLRC and DACBCLK are all inputs. In Master mode ADCLRC and ADCBCLK, DACLRC and DACBCLK are all outputs. The DAC’s and ADC can be in any combination of master or slave mode. Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume controls may be operated independently. In addition, a zero cross detect circuit is provided for each DAC for the digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. The software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC, and 256fs, 384fs, 512fs, and 768fs is provided for the ADC. In Slave mode selection between clock rates is automatically controlled. In master mode, the sample rate is set by control bits ADCRATE and DACRATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the DAC and from less than 32ks/s up to 96ks/s for the ADC, provided the appropriate master clock is input. The audio data interface supports right, left and I 2S interface formats along with a highly flexible DSP serial port interface. AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the ADC and DAC MCLK input pin(s) with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. The DAC master clock for WM8772EFT supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (DACLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz (for DAC operation only). The ADC master clock for WM8772EFT supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8772EFT has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master clocks must be synchronised with ADCLRC and DACLRC respectively, although the WM8772EFT is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8772EFT. |
Numéro de pièce similaire - WM8772_05 |
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Description similaire - WM8772_05 |
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