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NBSG16MNR2 Fiches technique(PDF) 3 Page - ON Semiconductor |
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NBSG16MNR2 Fiches technique(HTML) 3 Page - ON Semiconductor |
3 / 12 page NBSG16 http://onsemi.com 3 50 W 50 W VTD D D VTD VMM Q Q VBB VEE VCC Figure 3. Logic Diagram 75 k W 75 k W 36.5 KW Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD together AC−COUPLED Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. LVCMOS VMM should be connected to the unused complementary differential input. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (D, D) 75 k W Internal Input Pullup Resistor (D) 36.5 k W ESD Protection Human Body Model Machine Model > 2 kV > 100 V Moisture Sensitivity (Note 1) Pb Pkg Pb−Free Pkg FCBGA−16 QFN−16 Level 3 Level 1 N/A Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 167 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
Numéro de pièce similaire - NBSG16MNR2 |
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Description similaire - NBSG16MNR2 |
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