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MC14007UBD Fiches technique(PDF) 1 Page - ON Semiconductor

No de pièce MC14007UBD
Description  Dual Complementary Pair Plus Inverter
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
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MC14007UBD Fiches technique(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 8
1
Publication Order Number:
MC14007UB/D
MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multipurpose device consists of three N−Channel
and three P−Channel enhancement mode devices packaged to provide
access to each device. These versatile parts are useful in inverter
circuits, pulse−shapers, linear amplifiers, high input impedance
amplifiers, threshold detectors, transmission gating, and functional
gating.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4007A or CD4007UB
This device has 2 outputs without ESD Protection. Antistatic
precautions must be taken.
Pb−Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
−0.5 to +18.0
V
Vin, Vout Input or Output Voltage Range
(DC or Transient)
−0.5 to VDD +0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8 second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/°C from 65°C 5o 125°C.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
11
12
13
14
8
9
10
5
4
3
2
1
7
6
GATEC
S−PC
OUTC
D−PA
VDD
D−NA
S−NC
S−NB
GATEB
S−PB
D−PB
VSS
GATEA
D−NB
PIN ASSIGNMENT
D = DRAIN
S = SOURCE
MARKING
DIAGRAMS
1
14
PDIP−14
P SUFFIX
CASE 646
MC14007UBCP
AWLYYWWG
SOIC−14
D SUFFIX
CASE 751A
1
14
14007UG
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G= Pb−Free Indicator
SOEIAJ−14
F SUFFIX
CASE 965
1
14
MC14007UB
ALYWG
http://onsemi.com


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