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MC100LVELT23DR2G Fiches technique(PDF) 1 Page - ON Semiconductor |
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MC100LVELT23DR2G Fiches technique(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 14 1 Publication Order Number: MC100LVELT23/D MC100LVELT23 3.3 VDual Differential LVPECL/LVDS to LVTTL Translator Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal. The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a VCC of +3.3 V. Features • 2.0 ns Typical Propagation Delay • Maximum Frequency > 180 MHz • Differential LVPECL Inputs • PECL Mode Operating Range:VCC = 3.0 V to 3.8 V with GND = 0 V • 24 mA LVTTL Outputs • Flow Through Pinouts • Internal Pulldown and Pullup Resistors • Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAMS* KR23 ALYWG G SOIC−8 D SUFFIX CASE 751 1 8 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 http://onsemi.com KVT23 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 (Note: Microdot may be in either location) A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION |
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