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CAT28C64BLI-12T Fiches technique(PDF) 11 Page - Catalyst Semiconductor

No de pièce CAT28C64BLI-12T
Description  64K-Bit CMOS PARALLEL EEPROM
Download  13 Pages
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Fabricant  CATALYST [Catalyst Semiconductor]
Site Internet  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT28C64BLI-12T Fiches technique(HTML) 11 Page - Catalyst Semiconductor

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CAT28C64B
11
Doc. No. 1011, Rev. F
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection
on power-up in addition to the hardware protection
provided.
To allow the user the ability to program the device with
an EEPROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
CE
WE
tWP
AA
1555
55
0AAA
A0
1555
DATA
ADDRESS
tBLC
tWC
BYTE OR
PAGE
WRITES
ENABLED
Figure 12. Resetting Software Data Protection Timing
CE
WE
AA
1555
55
0AAA
DATA
ADDRESS
tWC
80
1555
AA
1555
55
0AAA
20
1555
SDP
RESET
DEVICE
UNPROTECTED
Speed
90: 90ns
12: 120ns
15: 150ns


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