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CAT24C16ZIT3 Fiches technique(PDF) 3 Page - Catalyst Semiconductor |
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CAT24C16ZIT3 Fiches technique(HTML) 3 Page - Catalyst Semiconductor |
3 / 17 page CAT24C01/02/04/08/16 3 Doc No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice A.C. CHARACTERISTICS(1) VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C. Symbol Parameter Standard Fast Units Min Max Min Max FSCL Clock Frequency 100 400 kHz tHD:STA START Condition Hold Time 4 0.6 μs tLOW Low Period of SCL Clock 4.7 1.3 μs tHIGH High Period of SCL Clock 4 0.6 μs tSU:STA START Condition Setup Time 4.7 0.6 μs tHD:DAT Data In Hold Time 0 0 μs tSU:DAT Data In Setup Time 250 100 ns tR SDA and SCL Rise Time 1000 300 ns tF(2) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time 4 0.6 μs tBUF Bus Free Time Between STOP and START 4.7 1.3 μs tAA SCL Low to Data Out Valid 3.5 0.9 μs tDH Data Out Hold Time 100 100 ns Ti(2) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns tSU:WP WP Setup Time 0 0 μs tHD:WP WP Hold Time 2.5 2.5 μs tWR Write Cycle Time 5 5 ms tPU(2, 3) Power-up to Ready Mode 1 1 ms Note: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF |
Numéro de pièce similaire - CAT24C16ZIT3 |
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Description similaire - CAT24C16ZIT3 |
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