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CAT25010ZI-GT3 Fiches technique(PDF) 9 Page - Catalyst Semiconductor |
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CAT25010ZI-GT3 Fiches technique(HTML) 9 Page - Catalyst Semiconductor |
9 / 18 page 9 CAT25010, CAT25020, CAT25040 Doc. No. 1006, Rev. S © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Figure 9. HOLD HOLD HOLD HOLD HOLD Timing Figure 8. Page Write Instruction Timing Note: Dashed Line= mode (1, 1) – –––– *X=0 for 25010, 25020 ; X=A8 for 25040 Note: Dashed Line= mode (1, 1) – –––– CS SCK HOLD SO tCD tHD tHD tCD tLZ tHZ HIGH IMPEDANCE SCK SI SO 00 00 00 10 BYTE ADDRESS Data Byte 1 012345678 13 14 15 16-23 24-31 Data Byte 2 Data Byte 3 Data Byte N CS OPCODE 7..1 0 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1 DATA IN HIGH IMPEDANCE A7 A0 X* Figure 10. WP WP WP WP WP Timing CS SCK WP WP tWPS tWPH Note: Dashed Line= mode (1, 1) – –––– must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and program- ming is continued. On power up, SO is in a high impedance. If an invalid opcode is received, no data will be shifted into the CAT25010/20/40, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. DESIGN CONSIDERATIONS The CAT25010/20/40 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. After power up, CS must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the CAT25010/20/40 goes into a write disable mode. CS |
Numéro de pièce similaire - CAT25010ZI-GT3 |
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Description similaire - CAT25010ZI-GT3 |
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