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MC100EP139DWR2G Fiches technique(PDF) 2 Page - ON Semiconductor

No de pièce MC100EP139DWR2G
Description  3.3V / 5V ECL 첨2/4, 첨4/5/6 Clock Generation Chip
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EP139DWR2G Fiches technique(HTML) 2 Page - ON Semiconductor

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MC10EP139, MC100EP139
http://onsemi.com
2
Figure 1. 20−Lead Pinout (Top View)
17
18
16
15
14
13
12
4
3
5678
9
Q0
11
10
Q1
Q1
Q2
Q2
Q3
Q3
VEE
19
20
2
1
VCC Q0
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK*, CLK*
ECL Differential Clock Inputs
EN*
ECL Sync Enable
MR*
ECL Master Reset
VBB
ECL Reference Output
Q0, Q1, Q0, Q1
ECL Differential B2/4 Outputs
Q2, Q3, Q2, Q3
ECL Differential B4/5/6 Outputs
DIVSELa*
ECL Frequency Select Input B2/4
DIVSELb0*
ECL Frequency Select Input B4/5/6
DIVSELb1
ECL Frequency Select Input B4/5/6
VCC
ECL Positive Supply
VEE
ECL Negative Supply
EP
Exposed Pad
*Pins will default low when left open.
1
2
3
4
5
15
14
13
12
11
67
8
9
10
20
19
18
17
16
Figure 1. QFN−20 Pinout (Top View)
Q0
Q1
Q1
VCC
Q0
VCC
Q2
Q2
Q3
Q3
VEE
CLK
CLK
MR
EN
DIVSELb0
VBB
VCC DIVSELb1DIVSELa
Exposed Pad
NOTE: The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to VEE.
MC10/100EP139


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