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MC100EP11DR2G Fiches technique(PDF) 2 Page - ON Semiconductor |
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MC100EP11DR2G Fiches technique(HTML) 2 Page - ON Semiconductor |
2 / 11 page MC10EP11, MC100EP11 http://onsemi.com 2 1 2 3 4 5 6 7 8 D VEE VCC Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Q0 D Q1 Q1 Q0 Table 1. PIN DESCRIPTION PIN D*, D** Q0, Q0, Q1, Q1 ECL Data Outputs FUNCTION ECL Data Inputs VCC VEE Negative Supply Positive Supply * Pins will default LOW when left open. ** Pins will default to high when left open. R1 R2 R1 EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg SOIC−8 TSSOP−8 DFN8 Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 73 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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