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74VCX16244DTR Fiches technique(PDF) 1 Page - ON Semiconductor

No de pièce 74VCX16244DTR
Description  Low?뭋oltage 1.8V/2.5V/3.3V 16?묪it Buffer
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

74VCX16244DTR Fiches technique(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 5
1
Publication Order Number:
74VCX16244/D
74VCX16244
Low−Voltage 1.8V/2.5V/3.3V
16−Bit Buffer
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74VCX16244 is an advanced performance, non−inverting
16−bit buffer. It is designed for very high−speed, very low−power
operation in 1.8 V, 2.5 V or 3.3 V systems.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.
The 74VCX16244 is nibble controlled with each nibble functioning
identically, but independently. The control pins may be tied together to
obtain full 16−bit operation. The 3−state outputs are controlled by an
Output Enable (OEn) input for each nibble. When OEn is LOW, the
outputs are on. When OEn is HIGH, the outputs are in the high
impedance state.
Features
Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V
3.6 V Tolerant Inputs and Outputs
High Speed Operation: 2.5 ns max for 3.0 V to 3.6 V
3.0 ns max for 2.3 V to 2.7 V
6.0 ns max for 1.65 V to 1.95 V
Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
±6 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±250 mA @ 125°C
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
All Devices in Package TSSOP are Inherently Pb−Free*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
TSSOP−48
DT SUFFIX
CASE 1201
1
48
VCX16244
AWLYYWW
1
48
Device
Package
Shipping
ORDERING INFORMATION
74VCX16244DT
TSSOP
(Pb−Free)
39 / Rail
74VCX16244DTR
TSSOP
(Pb−Free)
2500 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
http://onsemi.com


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