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TPA2012D2YZHT Fiches technique(PDF) 11 Page - Texas Instruments |
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TPA2012D2YZHT Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 20 page www.ti.com APPLICATION INFORMATION AVDD PVDD* Shutdown Control 0.1 mF SDR SDL PGND AGND INR+ INR− INL+ INL− OUTR+ OUTR− OUTL+ OUTL− 1 nF 0.1 mF DAC G0 G1 1 mF 0.1 mF 4.7 mF * For QFN, an additional capacitor is recomended for the second PVDD pin. To Battery 1 nF 1 nF 1 nF 0.1 mF 0.1 mF to Battery VDD OUTR+ GND INR+ 300 k C S 300 k G0 OUTR− OUTL+ OUTL− G1 INR− INL+ INL− Gain Adjust PWM Gain Adjust PWM H − Bridge H − Bridge Internal Oscillator Bias Circuitry Short−Circuit Protection Right Single−Ended Input CI CI SDR SDL CI CI Left Single−Ended Input to Battery VDD OUTR+ GND INR+ 300 k C S 300 k G0 OUTR− OUTL+ OUTL− G1 INR− INL+ INL− Gain Adjust PWM Gain Adjust PWM H − Bridge H − Bridge Internal Oscillator Bias Circuitry Short−Circuit Protection Right Differential Input CI CI Left Differential Input CI CI SDR SDL TPA2012D2 SLOS438C – DECEMBER 2004 – REVISED MARCH 2007 Figure 33. Typical Application Circuit Figure 35. TPA2012D2 Application Schematic Figure 34. TPA2012D2 Application Schematic With Single-Ended Input With Differential Input and Input Capacitors 11 Submit Documentation Feedback |
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