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FAN5099EMTCX Fiches technique(PDF) 11 Page - Fairchild Semiconductor |
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FAN5099EMTCX Fiches technique(HTML) 11 Page - Fairchild Semiconductor |
11 / 24 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5099 Rev. 1.1.3 11 PWM Operation Refer to Figure 21 for the PWM control mechanism. The FAN5099 uses the summing mode method of control to generate the PWM pulses. The amplified output of the current-sense amplifier is summed with an internally generated ramp and the combined signal is amplified and compared with the output of the error amplifier to get the pulse width to drive the high-side MOSFET. The sensed current from the previous cycle is used to modu- late the output of the summing block. The output of the summing block is also compared against the voltage threshold set by the RLIM resistor to limit the inductor cur- rent on a cycle-by-cycle basis. The controller facilitates external compensation for enhanced flexibility. Initialization When the PWM is disabled, the SW node is connected to GND through an internal 500 Ω MOSFET to slowly dis- charge the output. As long as the PWM controller is enabled, this internal MOSFET remains OFF. Soft-Start (PWM and LDO) When VCC exceeds the UVLO threshold and EN is high, the circuit releases SS and enables the PWM regulator. The capacitor connected to the SS pin and GND is charged by a 10µA internal current source, causing the voltage on the capacitor to rise. When this voltage exceeds 1.2V, all protection circuits are enabled. When this voltage exceeds 2.2V, the LDO output is enabled. The input to the error amplifier at the non-inverting pin is clamped by the voltage on the SS pin until it crosses the reference voltage. The time it takes the PWM output to reach regulation (TRise) is calculated using the following equation: (CSS is in μf) (EQ. 1) Oscillator Clock Frequency (PWM) The clock frequency on the oscillator is set using an external resistor, connected between R(T) pin and ground. The frequency follows the graph, as shown in Figure 18. The minimum clock frequency is 50kHz, which is when R(T) pin is left open. Select the value of R(T) as shown in the equation below. This equation is valid for all FOSC > 50kHz: (EQ. 2) where, FOSC is in Hz. For example, for FOSC = 80kHz, R(t) = 199kΩ. RRAMP Selection and Feedforward Operation The FAN5099 provides for input voltage feedforward compensation through RRAMP. The value of RRAMP effec- tively changes the slope of the internal ramp, minimizing the variation of the PWM modulator gain when input volt- age varies. The RRAMP effect on the current limit is explained in later sections. The RRAMP value can be approximated using the following equation: (EQ. 3) where FOSC is in Hz. For example, for FOSC = 80kHz and VIN = 12V, RRAMP = 2MΩ. Gate Drive Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals and provides necessary amplification, level shifting, and shoot-through protection. It also has functions that help optimize the IC performance over a wide range of oper- ating conditions. Since the MOSFET switching time can vary dramatically from device to device and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approxi- mately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. A low impedance path between the driver pin and the MOSFET gate is recommended for the adaptive dead- time circuit to work properly. Any delay along this path reduces the delay generated by the adaptive dead-time circuit, thereby increasing the chances for shoot-through. Protection In the FAN5099, the converter is protected against over- load, short-circuit, over-voltage, and under-voltage con- ditions. All of these extreme conditions generate an internal “fault latch” which shuts down the converter. For all fault conditions, both the high-side and the low-side drives are off, except in the case of OVP, where the low- side MOSFET is turned on until the voltage on the FB pin goes below 0.4V. The fault latch can be reset either by toggling the EN pin or recycling VCC to the chip. Over-Current Limit (PWM) The PWM converter is protected against overloading through a cycle-by-cycle current limit set by selecting RILIM resistor. An internal 10µA current source sets the threshold voltage for the output of the summing amplifier. When the summing amplifier output exceeds this thresh- old level, the current limit comparator trips and the PWM starts skipping pulses. If the current limit tripping occurs for 16 continuous clock cycles, a fault latch is set and the TRISE 810 2 – × CSS × = Rt () 410 7 × 6.25 FOSC × 2.99 10 5 × – ------------------------------------------------------------------k Ω = RRAMP V IN nom , () 1.8 – 6.3 8 – ×10 FOSC × --------------------------------------------K Ω = |
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