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M95040_06 Datasheet(Fiches technique) 18 Page - STMicroelectronics

Numéro de pièce M95040_06
Description  4 Kbit, 2 Kbit and 1 Kbit Serial SPI bus EEPROM with high speed Clock
Télécharger  42 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
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 18 page
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Instructions
M95040, M95020, M95010
18/42
6.3
Read Status Register (RDSR)
One of the major uses of this instruction is to allow the MCU to poll the state of the Write In
Progress (WIP) bit. This is needed because the device will not accept further WRITE or
WRSR instructions when the previous Write cycle is not yet finished.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current
state of the bits in the Status Register is shifted out, on Serial Data Out (Q). The Read Cycle
is terminated by driving Chip Select (S) High.
The Status Register may be read at any time, even during a Write cycle (whether it be to the
memory area or to the Status Register). All bits of the Status Register remain valid, and can
be read using the RDSR instruction. However, during the current Write cycle, the values of
the non-volatile bits (BP0, BP1) become frozen at a constant value. The updated value of
these bits becomes available when a new RDSR instruction is executed, after completion of
the Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write
In Progress (WIP)) are dynamically updated during the on-going Write cycle.
Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status
Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 3) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
Table 5.
Status Register format
b7
b0
1
1
1
1
BP1
BP0
WEL
WIP
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit




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