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L6730D Fiches technique(PDF) 7 Page - STMicroelectronics |
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L6730D Fiches technique(HTML) 7 Page - STMicroelectronics |
7 / 50 page L6730C - L6730D Pin connections and functions 7/50 3 Pin connections and functions Figure 2. Pins connection (top view) 1. In the L6730D the multifunction pin is: CC/OVP/UVLO. Table 3. Pins connection Pin n. Name Description 1 PGOOD DELAY Connecting a capacitor between this pin and ground a delay is introduced between the trigger of the internal PGOOD comparator and the external signal rising edge. No delay can be introduced on the falling edge of the PGOOD signal. The delay can be calculated with the following formula: 2 SYNCH It is a Master-Slave pin. Two or more devices can be synchronized by simply connecting the SYNCH pins together. The device operating with the highest FSW will be the Master. The Slave devices will operate with 180° phase shift from the Master. The best way to synchronize devices together is to set their FSW at the same value. If it is not used the SYNCH pin can be left floating. 3 SINK/OVP/UVLO L6730C CC/OVP/UVLO L6730D With this pin it is possible: – To enable-disable the sink mode current capability after SS (L6730C); – To enable-disable the constant current OCP after SS (L6730D); – To enable-disable the latch mode for the OVP; – To set the UVLO threshold for the 5V BUS and 12V BUS. The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 HTSSOP20 10 17 18 19 20 OSC SS/INH CO MP FB GN D SYNCH PGOOD DELAY TM ASK EAREF PGOOD PHASE HGATE BOOT VCC VCCDR LGATE OCL OCH PGND 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 HTSSOP20 10 17 18 19 20 OSC SS/INH CO MP FB GN D SYNCH PGOOD DELAY TM ASK EAREF PGOOD PHASE HGATE BOOT VCC VCCDR LGATE OCL OCH PGND SINK/OVP/UVLO HTSSOP20 QFN 4x4 24L () pF C PGDelay ⋅ = 5 . 0 [µs] |
Numéro de pièce similaire - L6730D |
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Description similaire - L6730D |
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