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BQ24740 Fiches technique(PDF) 5 Page - Texas Instruments |
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BQ24740 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 29 page www.ti.com bq24740 SLUS736 – DECEMBER 2006 Table 1. TERMINAL FUNCTIONS – 28-PIN QFN TERMINAL DESCRIPTION NAME NO. CHGEN 1 Charge enable active-low logic input. LO enables charge. HI disables charge. Adapter current sense resistor, negative input. An optional 0.1- µF ceramic capacitor is placed from ACN pin to AGND ACN 2 for common-mode filtering. An optional 0.1- µF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. ACP 3 Adapter current sense resistor, positive input. (See comments with ACN description) Low power mode detect active-high open-drain logic output. Place a 10-k Ω pullup resistor from LPMD pin to the pullup-voltage rail. Place a positive-feedback resistor from LPMD pin to LPREF pin for programming hysteresis (see LPMD 4 design example for calculation). The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The output is LO when IADAPT pin voltage is higher than LPREF pin voltage. Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The ACDET 5 IADAPT current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. Input overvoltage, ACOV, disables charge and ACDRV when ACDET > 3.1 V. ACOV does not latch Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC ACSET 6 to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the VDAC pin. Low power voltage set input. Connect a resistor divider from VREF to LPREF and AGND to program the reference for the LOPWR comparator. The LPREF-pin voltage is compared to the IADAPT-pin voltage and the logic output is given LPREF 7 on the LPMD open-drain pin. Connecting a positive-feedback resistor from LPREF pin to LPMD pin programs the hysteresis. Enable IADAPT to enter sleep mode; active-low logic input. Allows low Iq sleep mode when adapter not detected. Logic low turns off the Input Current Sense Amplifier (IADAPT) when adapter is not detected and ACDET pin is <0.6 IADSLP 8 V - allows lower battery discharge current. Logic high keeps IADAPT current-sense amplifier on when adapter is not detected and ACDET pin is <0.6 V - this allows measuring battery discharge current. Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the power AGND 9 pad underneath the IC. 3.3-V regulated voltage output. Place a 1- µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage VREF 10 could be used for ratiometric programming of voltage and current regulation. Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ, VDAC 11 SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pins to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to VADJ, SRSET, or ACSET. Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the VADJ 12 output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the default of 4.2 V per cell. Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed EXTPWR 13 threshold, OR input current is greater than 1.25 A with 10-m Ω sense resistor. Connect a 10-kΩ pullup resistor from EXTPWR pin to pullup supply rail. Synchronous mode voltage set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent ISYNSET 14 threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle). Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a IADAPT 15 100-pF or less ceramic decoupling capacitor from IADAPT to AGND. Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current SRSET 16 regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin. Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT BAT 17 pin to accurately sense the battery pack voltage. Place a 0.1- µF capacitor from BAT to AGND close to the IC to filter high-frequency noise. Charge current sense resistor, negative input. An optional 0.1- µF ceramic capacitor is placed from SRN pin to AGND SRN 18 for common-mode filtering. An optional 0.1- µF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. SRP 19 Charge current sense resistor, positive input. (See comments for SRN.) CELLS 20 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell. 5 Submit Documentation Feedback |
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Description similaire - BQ24740 |
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