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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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CXD1856R Fiches technique(PDF) 4 Page - Sony Corporation |
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CXD1856R Fiches technique(HTML) 4 Page - Sony Corporation |
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4 / 31 page  – 4 – CXD1856Q/R Horizontal sync signal. When using the built-in sync generator, the dot clock (DCLK) is frequency divided and output. When not using the sync generator, this pin is an input. Vertical sync signal. When using the built-in sync generator, the dot clock (DCLK) is frequency divided and output. When not using the built-in sync generator, this pin is an input. Field identification signal (FID) and horizontal sync phase reference signal (FHREF). The signal to be used is set in the register. When set to FID, this pin is an output if using the built-in sync generator, and an input if not using the built-in sync generator. High corresponds to odd fields. When set to FHREF, this pin outputs the signal obtained by frequency dividing XTL0. When XTL0 is 8fsc, this signal is equivalent to the HSYNC cycle, and can be used for phase comparison with the HSYNC signal. Composite blanking signal (CBLNK) and fsc signal. The signal to be used is set in the register. When set to CBLNK, this pin is an output if using the built-in sync generator, and an input if not using the built-in sync generator. When set to fsc, this pin outputs the signal obtained by frequency dividing XTL0. The frequency division ratio can be selected from 1/8 or 1/16. Composite sync signal obtained by frequency dividing DCLK. This pin cannot be input. Sync generator reset signal input. The built-in sync generator is initialized by setting this pin low. Output for clock obtained by frequency dividing XTL0. The frequency division ratio can be selected from 1, 1/2, 1/4 or 1/8. Audio digital output. Audio serial data output to DAC. L/R clock output to DAC. Bit clock output to DAC. Audio interface clock input. Input 256fs (11.2896MHz), 384fs (16.9344MHz), 512fs (22.5792MHz), or 768fs (33.8688MHz), etc. Master clock for CD-ROM and audio decoders. Input the clock to XTL2I or connect an oscillator between XTL2I and XTL2O. The recommended frequency is 45MHz. Note that this clock is for the internal circuits, and the input and output are not synchronized. C2 pointer input from CD-DSP. Indicates that the DATI input contains an error. LR clock input from CD-DSP. Indicates the L or R channel of DATI. Serial data input from CD-DSP. Bit clock input from CD-DSP. This clock strobes the DATI input. Digital data input from CD-DSP. Chip select signal input during register access. Wait signal output during register access. Host interface operates in parallel mode and the wait signal is output by the register switching during DRAM access. This pin functions as an open drain, and should therefore be pulled up. It should be pulled up when the host interface operates in serial mode as well. 92 93 94 95 96 97 98 99 100 101 102 103 106 107 109 110 111 112 113 114 115 HSYNC VSYNC FID/FHREF CBLNK/ FSC CSYNC XSGRST CLK0O DOUT DATO LRCO BCKO FSXI XTL2O XTL2I C2PO LRCI DATI BCKI DOIN XHCS XHDT I/O I/O I/O I/O O I O O O O O I O I I I I I I I I/O Pin No. Symbol I/O Description |
Numéro de pièce similaire - CXD1856R |
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Description similaire - CXD1856R |
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