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CS61884-IQ Fiches technique(PDF) 6 Page - Cirrus Logic |
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CS61884-IQ Fiches technique(HTML) 6 Page - Cirrus Logic |
6 / 22 page CDB61884 6 DS485DB1 2.3 Operating Mode Selection The operating mode for the CS61884 can be select- ed by setting switch S15 to one of the positions shown in Figure 4. 2.4 Line Interface Connections In both hardware and host modes, the receive line signals (RTIP/RRING) are connected to the bind- ing post labeled RXT 0-7 and RXR 0-7. The line signals from the binding posts are coupled to the device through two octal transformers (T1 and T9). The receivers of the device use external resistors to match the line impedance. These resistors are sock- eted for ease in changing the line impedance, for in- ternal or external line impedance matching. During internal line impedance matching mode, the resis- tor values are the same (15 Ω) for all modes of op- eration: E1 75 Ω, E1 120 Ω or T1/J1 100 Ω. During external line impedance matching mode the receiv- er resistors need to be change to the values shown in Table 1. The jumpers listed in Table 2 areusedtoplace or bypass 1 K Ω protection resistors in series with the receive line signals (RTIP/RRING). These resis- tors are used for receiver protection while in exter- nal line impedance matching mode and should not be used during internal line impedance matching mode. To place the 1 K Ω resistors in series with the receive line signals, remove the short blocks from each of the jumpers described in Table 2. To by- pass the 1 K Ω resistors, place a short block on each jumper shown in Table 2. The transmit line signals (TTIP/TRING) from the device are coupled to the line binding post (TXT 0- 7 and TXR 0-7) through two octal transformers (T1 and T9). External protection circuitry such as di- odes or chokes are recommended for protection. For further information on line protection refer to Application Note AN34, “Secondary Line Protec- tion for T1 and E1 Line Cards” (AN34REV1 SEP '94). 2.5 TXOE Selection Jumper J23 is used to enable or High-Z all eight transmitters in both hardware and host mode. A shorting block on Jumper J23 places all the trans- Table 1. External Impedance Resistor Values T1/J1 100 Ω E1 75 Ω E1 120 Ω 12.5 Ω 9.31 Ω 15 Ω S15 Hardware Serial Host Parallel Host Selects Hardware Mode Selects Serial Host Mode Selects Parallel Host Mode MODE S15 Hardware Serial Host Parallel Host S15 Hardware Serial Host Parallel Host MODE MODE Figure 4. Hardware/Host Mode Selection Table 2. Protection Resistor Selection Jumper Description J29 Channel 0 RRING signal J30 Channel 0 RTIP Signal J37 Channel 1 RTIP Signal J38 Channel 1 RRING Signal J46 Channel 2 RRING Signal J47 Channel 2 RTIP Signal J54 Channel 3 RTIP Signal J55 Channel 3 RRING Signal J65 Channel 4 RRING Signal J66 Channel 4 RTIP Signal J73 Channel 5 RTIP Signal J74 Channel 5 RRING Signal J81 Channel 6 RRING Signal J82 Channel 6 RTIP Signal J89 Channel 7 RTIP Signal J90 Channel 7 RRING Signal |
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Description similaire - CS61884-IQ |
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