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CDB43L21 Fiches technique(PDF) 9 Page - Cirrus Logic |
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CDB43L21 Fiches technique(HTML) 9 Page - Cirrus Logic |
9 / 63 page DS723A1 9 CS43L21 2. TYPICAL CONNECTION DIAGRAMS 1 µF +1.8 V or +2.5 V 1 µF VQ FILT+ 0.1 µF 1 µF DGND VL 0.1 µF +1.8 V, +2.5 V or +3.3 V SCL/CCLK SDA/CDIN RESET 2 k Ω See Note 1 LRCK AGND AD0/CS MCLK SCLK 0.1 µF VA_HP VD SDIN CS43L21 2 k Ω 1 µF +1.8 V or +2.5 V AOUTB AOUTA 470 Ω 470 Ω C C Rext Rext See Note 2 Note 1: Resistors are required for I²C control port operation For best response to Fs/2 : () 470 4 470 × + = ext ext R Fs R C π This circuitry is intended for applications where the CS43L21 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. Note 2 : Digital Audio Processor 0.1 µF VA Headphone Out Left & Right Line Level Out Left & Right Speaker Driver FLYP FLYN VSS_HP GND_HP 1 µF 51.1 Ω 0.022 µF 1 µF ** ** * *Use low ESR ceramic capacitors. See Note 3 Note 3: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . 1.5 µF 1.5 µF See Note 4 Note 4 : Larger capacitors, such as 1.5 µF, improves the charge pump performance (and subsequent THD+N) at the full scale output power achieved with gain (G) settings greater than default. ** ** Figure 1. Typical Connection Diagram (Software Mode) |
Numéro de pièce similaire - CDB43L21 |
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Description similaire - CDB43L21 |
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