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AD9396KSTZ-150 Fiches technique(PDF) 10 Page - Analog Devices

No de pièce AD9396KSTZ-150
Description  Analog/DVI Dual-Display Interface
Download  48 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9396KSTZ-150 Fiches technique(HTML) 10 Page - Analog Devices

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AD9396
Rev. 0 | Page 10 of 48
Mnemonic
Description
DATA ENABLE
Data Enable that defines valid video. Can be received in the signal or generated by the AD9396.
CTL(3 to 0)
Control 3, Control 2, Control 1, and Control 0 are output from the DVI stream. Refer to the DVI 1.0 specification for
explanation.
SERIAL PORT
SDA
Serial Port Data I/O for Programming AD9396 Registers—I2C® Address is 0x98.
SCL
Serial Port Data Clock for Programming AD9396 Registers.
DDCSDA
Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76.
DDCSCL
Serial Port Data Clock for HDCP Communications to Transmitter.
MDA
Serial Port Data I/O to EEPROM with HDCP Keys—I2C Address is 0xA0.
MCL
Serial Port Data Clock to EEPROM with HDCP Keys.
DATA OUTPUTS
Red [7:0]
Data Output, Red Channel.
Green [7:0]
Data Output, Green Channel.
Blue [7:0]
Data Output, Blue Channel.
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the
color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is
shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is
maintained.
DATA CLOCK
OUTPUT
DATACK
Data Clock Output.
This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output
clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2×
frequency pixel clock and a 90° phase shifted pixel clock) and they are produced either by the internal PLL clock
generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted
via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register.
When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.
POWER SUPPLY1
VD (3.3 V)
Analog Power Supply.
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
VDD
(1.8 V to 3.3 V)
Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the VD pins, so take care to minimize output noise
transferred into the sensitive analog circuitry. If the AD9396 is interfacing with lower voltage logic, VDD may be
connected to a lower supply voltage (as low as 1.8 V) for compatibility.
PVDD (1.8 V)
Clock Generator Power Supply.
The most sensitive portion of the AD9396 is the clock generation circuitry. These pins provide power to the clock PLL
and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.
DVDD (1.8 V)
Digital Input Power Supply.
This supplies power to the digital logic.
GND
Ground.
The ground return for all circuitry on-chip. It is recommended that the AD9396 be assembled on a single solid ground
plane, with careful attention to ground current paths.
1 The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD.


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