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AD8188Z-EVALZ Fiches technique(PDF) 6 Page - Analog Devices |
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AD8188Z-EVALZ Fiches technique(HTML) 6 Page - Analog Devices |
6 / 24 page AD8188/AD8189 Rev. 0 | Page 6 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 AD8188/ AD8189 TOP VIEW (Not to Scale) VCC VCC DVCC VEE OUT2 VCC OUT1 VEE OUT0 VCC OE IN0A IN0B VEE IN1B VEE IN2B VEE VCC IN2A VREF IN1A DGND SEL A/B Figure 4. AD8188/AD8189 Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 IN0A Input, High-ZIN. Routed to OUT0 when A is selected. 2 DGND Ground Reference for Digital Control Circuitry. 3 IN1A Input, High-ZIN. Routed to OUT1 when A is selected. 4 VREF AD8188: Bypass point for internal reference. Does not affect dc level of output. AD8189: Input to reference buffers for all channels. Can be used to offset the outputs. 5 IN2A Input, High-ZIN. Routed to OUT2 when A is selected. 6, 13, 17, 21, 24 VCC Positive Analog Supply. Nominally 5 V higher than VEE. 7, 9, 11, 15, 19 VEE Negative Analog Supply. 8 IN2B Input, High-ZIN. Routed to OUT2 when B is selected. 10 IN1B Input, High-ZIN. Routed to OUT1 when B is selected. 12 IN0B Input, High-ZIN. Routed to OUT0 when B is selected. 14 DVCC Positive Supply for Digital Control Circuitry. Referenced to DGND. 16 OUT2 Output. Can connect to IN2A, IN2B, or disable. 18 OUT1 Output. Can connect to IN1A, IN1B, or disable. 20 OUT0 Output. Can connect to IN0A, IN0B, or disable. 22 SEL A/B Logic high selects the three A inputs. Logic low selects the three B inputs. 23 OE Output Enable. Logic high enables the three outputs. Table 5. Truth Table SEL A/B OE OUT 0 0 High-Z 1 0 High-Z 1 1 INxA 0 1 INxB |
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