Preliminary Technical Data

AD7766

Rev. PrD | Page 5 of 18

TIMIMG DIAGRAMS

MCLK

DRDY

1

8*n

1

8*n

Figure 2.DRDY versus MCLK TimingDiagram. For AD7766 n=1(Decimate by8), AD7766-1 n=2(Decimate by 16), AD7766-2 n = 4(Decimate by 32).

SDO

MSB

LSB

SCLK

CS

DRDY

D22

1

23

D21

D20

D1

Figure 3.Serial timing diagram, reading data using CS

SDO

MSB

LSB

SCLK

DRDY

1

24

DATA

INVALID

DATA

INVALID

D22

23

D21

D20

D1

CS = 0

Figure 4.Serial timing diagram, reading data setting CS logic low.