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AD5625RBCPZ-REEL7 Fiches technique(PDF) 7 Page - Analog Devices |
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AD5625RBCPZ-REEL7 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 32 page Preliminary Technical Data AD5625R/AD5645R/AD5665R, AD5625/AD5665 Rev. PrA. | Page 7 of 32 Limit at TMIN, TMAX Parameter Conditions2 Min Max Unit Description t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, CB = 400 pF 20 80 ns tSP4 Fast mode 0 50 ns Pulse width of spike suppressed High speed mode 0 10 ns 1See Figure 2. High speed mode timing specification applies only to the AD5625BRUZ-2 and AD5665BRUZ-2. 2CB refers to the capacitance on the bus line. 3The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode. Figure 2. 2-Wire Serial Interface Timing Diagram |
Numéro de pièce similaire - AD5625RBCPZ-REEL7 |
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Description similaire - AD5625RBCPZ-REEL7 |
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