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AD5360 Fiches technique(PDF) 1 Page - Analog Devices

No de pièce AD5360
Description  16-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5360 Fiches technique(HTML) 1 Page - Analog Devices

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16-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
Preliminary Technical Data
AD5360/AD5361
Rev. P
rF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2006 Analog Devices, Inc. All rights reserved.
FEATURES
16-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V digital interface
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical Line Cards
FUNCTIONAL BLOCK DIAGRAM
5360-0001
CONTROL
REGISTER
STATE
MACHINE
n
POWER-ON
RESET
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
AD5360/
AD5361
SERIAL
INTERFACE
8
BIN/2SCOMP
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
n
n
n
DAC 0
REGISTER
n
n
8
8
n
n
n
n
TO
MUX 2's
MUX
1
A/B SELECT
REGISTER
X1A REGISTER
X1B REGISTER
MREGISTER
CREGISTER
n
MUX
2
X2A REGISTER
X2B REGISTER
OFS1
REGISTER
14
14
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OFFSET
DAC 1
BUFFER
n
n
n
DAC 7
REGISTER
n
n
n
n
n
n
MUX
1
X1A REGISTER
X1B REGISTER
MREGISTER
CREGISTER
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 7
·
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GROUP 1
VREF0
SIGGND0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
LDAC
DVCC
VDD
VSS AGND DNGD
n
n
n
DAC 0
REGISTER
n
n
8
8
n
n
n
n
TO
MUX 2's
MUX
1
A/B SELECT
REGISTER
X1A REGISTER
X1B REGISTER
MREGISTER
CREGISTER
n
MUX
2
X2A REGISTER
X2B REGISTER
OFS0
REGISTER
14
14
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OFFSET
DAC 0
BUFFER
GROUP 0
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n
n
n
DAC 7
REGISTER
n
n
n
n
n
n
MUX
1
X1A REGISTER
X1B REGISTER
MREGISTER
CREGISTER
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 7
BUFFER
VREF1
AD5360, n = 16
AD5361, n = 14
GPIO
REGISTER
TEMP
SENSOR
TEMP_OUT
PEC
MON_IN0
MON_IN1
GPIO
MON_OUT
VOUT0 -
VOUT15
MUX
6
2
Figure 1.
AD5360/AD5361—Protected by U.S. Patent No. 5,969,657; other patents pending


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