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ADT7473 Fiches technique(PDF) 5 Page - Analog Devices |
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ADT7473 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 76 page ADT7473 Rev. A | Page 5 of 76 Min Typ Max Unit Test Conditions/Comments Parameter DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH 2.0 V 3.6 V Maximum input voltage Input Low Voltage, VIL 0.8 V −0.3 V Minimum input voltage Hysteresis 0.5 V p-p DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+ Input High Voltage, VIH 0.75 × VCC V Input Low Voltage, VIL 0.4 V DIGITAL INPUT CURRENT Input High Current, IIH ±1 µA VIN = VCC Input Low Current, IIL ±1 µA V = 0 Input Capacitance, CIN 5 IN pF SERIAL BUS TIMING See Figure 2 Clock Frequency, fSCLK 10 Hz 400 k Glitch Immunity, tSW 50 ns Bus Free Time, t 4.7 µs BUF SCL Low Time, tLOW 4.7 µs SCL High Time, tHIGH 4.0 50 µs SCL, SDA Rise Time, tr 1,000 ns SCL, SDA Fall Time, tf 300 µs Data Setup Time, tSU;DAT 250 ns Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be optionally disabled ll voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA = 25°C and represent most likely parametric norm. Logic inputs accept input igh voltages up to VMAX, even when device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. TIMING DIAGRAM Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested. 1 A h SCL SDA PS SP tBUF tHD; STA tHD; DAT tSU; DAT tF tR tLOW tSU; STA tHIGH tHD; STA tSU; STO Figure 2. Serial Bus Timing Diagram |
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