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CS51220EDR16 Fiches technique(PDF) 11 Page - ON Semiconductor

No de pièce CS51220EDR16
Description  Feed Forward Voltage Mode PWM Controller with Programmable Synchronization
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS51220EDR16 Fiches technique(HTML) 11 Page - ON Semiconductor

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11
The effect of the soft hiccup can be observed in Figure 9,
which shows the output voltage as load increases. The output
is maintained at the regulation value of 5.0 V until it goes into
current limit. At the point of overcurrent inception (A), the
current limit level changes to a lower level (B). The
switchback to a lower current limit level can be seen as the
bottom curve in Figure 9.
0
Load Current (A)
Figure 9. Overcurrent In a 5.0 V Output
Converter Using Soft Hiccup
46
6
2
0
2
5
4
3
1
A
B
A typical overload scenario is shown in Figure 10. The top
trace is the voltage on the Soft Start (SS) pin. The initial high
discharge rate can be seen transitioning to a 40 ms discharge
period. During this period the ISET establishes a lower
current limit level. The bottom trace shows the output
current. The initial current spike is the output capacitors
discharging. The next level around 4.0 A is the short circuit
current level set by the ISET current. The output then turns
off allowing the current to reduce to a level that does not
cause overcurrent pulses. This releases the SS pin to ramp
back up. During ramp up, the output is still shorted as noted
by the 8.0 A current level. When SS reaches the 2.9 V level,
the short is again recognized and ISET is turned back on
shifting the short circuit current level.
Figure 10. Over−Load Current and
Soft Start Waveforms
The middle trace is a digitizing ‘scope trace of the current
sense line. The scope interprets the voltages as an average
voltage. This voltage is actually a narrow duty cycle peak
voltage representing the peak current level in the switching
transistor. The actual peak voltages can be seen in the Figure
11. The peaks are 0.85 V at full load, reducing to 0.6 V peak
at the reduced short circuit level. The 1.1 V peak is the full
short circuit current while SS ramps back up. The 0.32 V level
is the normal load resistance, while ISET is still on. The 1.0 V
surge is created by ramp up into a normal 5.0 A load and
followed by the 0.85 V at normal load.
Figure 11. Over−Load Current and
ISENSE Voltage
Peak Detect Setting
Oscillator and Synchronization
The switching frequency is programmable through a
capacitor connected to the CT pin. When the CT pin voltage
reaches peak voltage (2.0 V), the internal discharge current
discharges the CT capacitor and VO stays low. When the CT
voltage declines to valley voltage (0.9 V), the current source
toggles to charge current and ramps up the CT pin. This starts
a new switching cycle. The duty cycle of the oscillator
determines the maximum PWM duty cycle.
The switching frequency of the IC can be synchronized to
an external frequency presented to the SYNCI pin. When
pulses with amplitude over SYNCI input threshold are
detected, the CT pin immediately ramps down the external
capacitor and the VO pin is forced low. A new switching
cycle begins when the CT pin reaches valley voltage. During
synchronization, the oscillator charge current is reduced by
80 μA, while discharge current is increased by 80 μA. This
effectively slows down the internal oscillator to avoid any
race condition with the sync frequency. As a result, the sync
frequency can be either higher or lower than the internal
oscillator frequency. CS51220 is able to synchronize up to
500 kHz and down to 25% below CT frequency. The
maximum duty cycle clamp is raised to 92% in
synchronization mode. The original oscillator frequency is
restored upon the removal of sync pulses.


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