Moteur de recherche de fiches techniques de composants électroniques |
|
ADE7752BARW Fiches technique(PDF) 5 Page - Analog Devices |
|
ADE7752BARW Fiches technique(HTML) 5 Page - Analog Devices |
5 / 27 page Preliminary Technical Data ADE7752B Rev. PrA | Page 5 of 27 TIMING CHARACTERISTICS VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. Table 2. Parameter1,2 Conditions Specification Unit t1 3 F1 and F2 pulse width (logic high) 120 ms t2 Output pulse period (see the Transfer Function section) See Figure 2 sec t3 Time between F1 falling edge and F2 falling edge 1/2 t2 sec t43, 4 CF pulse width (logic high) 90 ms t55 CF pulse period (see the Transfer Function section) See Table 7 sec t6 Minimum time between F1 and F2 pulse 4/CLKIN sec 1 Sample tested during initial release and after any redesign or process changes that might affect this parameter. 2 See Figure 2. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies (see the Frequency Outputs section). 4 CF is not synchronous to F1 or F2 frequency outputs. 5 The CF pulse is always 1 μs in the high frequency mode (see the Frequency Outputs section). F1 F2 CF t1 t6 t2 t3 t4 t5 Figure 2. Timing Diagram for Frequency Outputs |
Numéro de pièce similaire - ADE7752BARW |
|
Description similaire - ADE7752BARW |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |