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Timing Interval
T#
Min.
Max.
Units
Command Byte Write Timing
~HostSlct Hold Time
T6
15
2000 (note 3)
nS
~HostSlct Setup Time
T7
10
nS
HostCmd Setup Time
T8
10
nS
Host Cmd Hold Time
T9
25
nS
HostRdy Delay Time
T13
70
nS
~HostWrite Pulse Width
T14
50
nS
Write Data Setup Time
T15
35
nS
Write Data Hold Time
T16
30
nS
Data Word Read Timing
~HostSlct Hold Time
T6
15
2000 (note 3)
nS
~HostSlct Setup Time
T7 (read only)
- 20
nS
HostCmd Setup Time
T8 (read only)
- 20
nS
HostCmd Hold Time
T9
25
nS
Read Data Access Time
T10
50
nS
Read Data Hold Time
T11
10
nS
~HostRead high to HI-Z Time
T12
50
nS
HostRdy Delay Time
T13
70
nS
Read Recovery Time
T17
60
nS
Data Word Write Timing
~HostSlct Hold Time
T6
15
2000 (note 3)
nS
~HostSlct Setup Time
T7
10
nS
HostCmd Setup Time
T8
10
nS
HostCmd Hold Time
T9
25
nS
HostRdy Delay Time
T13
70
nS
~HostWrite Pulse Width
T14
50
nS
Write Data Setup Time
T15
35
nS
Write Data Hold Time
T16
30
nS
Write Recovery Time
T18
60
nS
note 1
~HostSlct and HostCmd may optionally be de-asserted if setup and hold times are met.
note 2
Chip-set performance figures and timing information valid at Fclk = 25.0 only. For timing information & performance parameters at Fclk <
25.0 Mhz, call PMD.
note 3
Two micro seconds maximum to release interface before chip set responds to command
note 4
ClkOut from CP is 1/4 frequency of ClkIn (CP chip).