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74AUP1G0832GW Fiches technique(PDF) 5 Page - NXP Semiconductors |
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74AUP1G0832GW Fiches technique(HTML) 5 Page - NXP Semiconductors |
5 / 19 page 74AUP1G0832_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 — 26 January 2006 5 of 19 Philips Semiconductors 74AUP1G0832 Low-power 3-input AND-OR gate 9. Limiting values [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. Fig 5. 2-input AND gate Fig 6. 2-input OR gate Fig 7. 2-input OR gate Fig 8. 3-input gate with the Boolean function: Y = (A × B) + C 001aad944 1 2 3 6 5 4Y VCC B A A B Y 001aad945 1 2 3 6 5 4Y Y C B B C VCC 001aad946 1 2 3 6 5 4Y Y C A A C VCC 001aad947 1 2 3 6 5 4Y C A B VCC A B C Y Table 7: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V IIK input clamping current VI <0V - −50 mA VI input voltage [1] −0.5 +4.6 V IOK output clamping current VO <0V - −50 mA VO output voltage active mode and Power-down mode [1] −0.5 +4.6 V IO output current VO =0 VtoVCC - ±20 mA ICC quiescent supply current - +50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C [2] - 250 mW |
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