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AD5259BRMZ100 Fiches technique(PDF) 4 Page - Analog Devices

No de pièce AD5259BRMZ100
Description  Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer
Download  14 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5259BRMZ100 Fiches technique(HTML) 4 Page - Analog Devices

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AD5259
Preliminary Technical Data
Rev. PrJ 7/22/04 | Page 4 of 14
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted.)
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications Apply to All Parts)
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus Free Time between STOP and START
t1
1.3
µs
tHD;STA Hold Time (Repeated START)
t2
After this period, the first clock pulse is
generated.
0.6
µs
tLOW Low Period of SCL Clock
t3
1.3
µs
tHIGH High Period of SCL Clock
t4
0.6
µs
tSU;STA Setup Time for Repeated START Condition
t5
0.6
µs
tHD;DAT Data Hold Time
t6
0
0.9
µs
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300
ns
tR Rise Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Setup Time for STOP Condition
t10
0.6
µs
t1
SCL
SDA
PS
P
t3
t2
t8
t9
t8
t9
t4
t5
t7
t6
t10
Figure 4. I2C Interface Timing Diagram


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