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NB4L6254 Fiches technique(PDF) 2 Page - ON Semiconductor |
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NB4L6254 Fiches technique(HTML) 2 Page - ON Semiconductor |
2 / 9 page NB4L6254 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345 678 24 23 22 21 20 19 18 17 16 GND VCC OEA CLK0 CLK0 VCC SEL0 GND QB2 QB2 QB1 QB1 QB0 QB0 QA2 QA2 VCC VCC OEB CLK1 QA1 VCC GND VCC QA1 VCC QA0 QA0 GND SEL1 CLK1 VCC Figure 2. Pin Configuration (Top View) LQFP−32 Table 1. PIN CONFIGURATION Pin Name I/O Description CLK0, CLK0 LVPECL Input Differential reference clock signal input 0. CLK1, CLK1 LVPECL Input Differential reference clock signal input 1. OEAb, OEB LVCMOS Input Output Enable SEL0, SEL1 LVCMOS Input Clock Switch Select QA[0−2], QA[0−2] QB[0−2], QB[0−2] LVPECL Output Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 W resistor to VCC – 2.0 V. GND Power Supply Negative Supply Voltage VCC Power Supply Positive supply voltage. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Table 2. FUNCTION TABLE Control Default 0 1 OEA 0 QA[0−2], QA[0−2] are active. Deassertion of OEA can be asynchronous to the reference clock without generation of output runt pulses QA[0−2] = L, QA[0−2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses OEB 0 QB[0−2], QB[0−2] are active. Deassertion of OEB can be asynchronous to the reference clock without generation of output runt pulses QB[0−2] = L, QB[0−2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses SEL0, SEL1 00 Refer to Table 3 Refer to Table 3 Table 3. CLOCK SELECT CONTROL SEL0 SEL1 CLK0 Routed To CLK1 Routed to Application Mode 0 0 QA[0:2] and QB[0:2] − 1:6 Fanout of CLK0 0 1 − QA[0:2] and QB[0:2] 1:6 Fanout of CLK1 1 0 QA[0:2] QB[0:2] Dual 1:3 Buffer 1 1 QB[0:2] QA[0:2] Dual 1:3 Buffer (Crossed) |
Numéro de pièce similaire - NB4L6254 |
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Description similaire - NB4L6254 |
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