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AD9411BSV-170 Fiches technique(PDF) 9 Page - Analog Devices |
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AD9411BSV-170 Fiches technique(HTML) 9 Page - Analog Devices |
9 / 28 page AD9411 Rev. A | Page 9 of 28 Table 6. Pin Function Descriptions Pin No. Mnemonic Function 1 S5 Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential; GND sets FS = 1.536 V p-p differential. 2, 42–46,49–52 DNC Do Not Connect. 3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 AGND Analog Ground. AGND and DRGND should be tied together to a common ground plane. 5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 AVDD 3.3 V Analog Supply. 6 S1 Data Format Select. GND = binary; AVDD = twos complement. 7 LVDSBIAS Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to ground. 10 SENSE Reference Mode Select Pin. Float for internal reference operation. 11 VREF 1.235 V Reference Input/Output. Function depends on SENSE. 21 VIN+ Analog Input. True. 22 VIN– Analog Input. Complement. 36 CLK+ Clock Input. True (LVPECL levels). 37 CLK– Clock Input. Complement (LVPECL levels). 47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 48, 53, 61, 67, 74, 82 DRGND Digital Output Ground. AGND and DRGND should be tied together to a common ground plane. 56 D0+ D0 True Output Bit. 57 D1– D1 Complement Output Bit. 58 D1+ D1 True Output Bit. 59 D2– D2 Complement Output Bit. 60 D2+ D2 True Output Bit. 63 DCO– Data Clock Output. Complement. 64 DCO+ Data Clock Output. True. 65 D3– D3 Complement Output Bit. 66 D3+ D3 True Output Bit. 68 D4– D4 Complement Output Bit. 69 D4+ D4 True Output Bit. 70 D5– D5 Complement Output Bit. 71 D5+ D5 True Output Bit. 72 D6– D6 Complement Output Bit. 73 D6+ D6 True Output Bit. 76 D7– D7 Complement Output Bit. 77 D7+ D7 True Output Bit. 78 D8– D8 Complement Output Bit. 79 D8+ D8 True Output Bit. 80 D9– D9 Complement Output Bit. 81 D9+ D9 True Output Bit. 84 OR– Overrange Complement Output Bit. 85 OR+ Overrange True Output Bit. |
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