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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD9980KSTZ-95 Fiches technique(PDF) 1 Page - Analog Devices |
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AD9980KSTZ-95 Fiches technique(HTML) 1 Page - Analog Devices |
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1 / 44 page  High Performance 8-Bit Display Interface AD9980 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. FEATURES 95 MSPS maximum conversion rate 9% or less p-p PLL clock jitter at 95 MSPS Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable output drive strength Odd/even field detection External clock input Regenerated Hsync output Programmable output high impedance control Hsyncs per Vsyncs counter Pb-free package APPLICATIONS Advanced TVs Plasma display panels LCD TV HDTV RGB graphics processing LCD monitors and projectors Scan converters FUNCTIONAL BLOCK DIAGRAM CB/CR/REDOUT Y/GREENOUT CB/BLUEOUT SYNC PROCESSING PLL POWER MANAGEMENT SOGOUT O/E FIELD HSOUT VSOUT/A0 VOLTAGE REFS SERIAL REGISTER SDA SCL FILT CLAMP EXTCLK/COAST HSYNC2 HSYNC1 AD9980 CLAMP 8 CLAMP 8 CLAMP 8 8 8 8 8 8 8 8-BIT ADC REFHI REFCM REFLO DTACK AUTO OFFSET AUTO OFFSET AUTO OFFSET 8-BIT ADC 8-BIT ADC PGA PGA PGA 2:1 MUX PR/REDIN0 PR/REDIN1 2:1 MUX Y/GREENIN0 Y/GREENIN1 2:1 MUX PB/BLUEIN0 PB/BLUEIN1 2:1 MUX VSYNC2 VSYNC1 2:1 MUX SOGIN2 SOGIN1 2:1 MUX Figure 1. GENERAL DESCRIPTION The AD9980 is a complete, 8-bit, 95 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 95 MSPS encode rate capability and full- power analog bandwidth of 200 MHz supports all HDTV video modes and graphics resolutions up to XGA (1024 × 768 at 85 Hz). The AD9980 includes a 95 MHz triple ADC with an internal reference, a phase-locked loop (PLL), programmable gain, offset, and clamp controls. The user provides only 3.3 V and 1.8 V power supplies and an analog input. Three-state CMOS outputs may be powered from 1.8 V to 3.3 V. The AD9980’s on-chip PLL generates a sample clock from the three-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 95 MHz. PLL clock jitter is 9% or less p-p typical at 95 MSPS. With internal Coast generation, the PLL maintains its output frequency in the absence of sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained. The auto-offset feature can be enabled to automatically restore the signal reference levels and to automatically calibrate out any offset differences between the three channels. The AD9980 also offers full sync processing for composite sync and sync-on- green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. Fabricated in an advanced CMOS process, the AD9980 is provided in a space-saving, 80-pin, Pb-free, LQFP surface mount plastic package. It is specified over the 0°C to +70°C temperature range. |
Numéro de pièce similaire - AD9980KSTZ-95 |
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Description similaire - AD9980KSTZ-95 |
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