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Normal switching

PWM

LGATE

UGATE

3 −State

window

90 %

10 %

tDLL

50 %

tFL

50 %

tPWM_MIN

tDTU

90 %

10 %

tRU

90 %

10 %

tDLU

tFU

tDTL

90 %

10 %

tRL

tHLD_R

90 %

10 %

90 %

90 %

tHLD_F

Enter into

3 −State

at PWM rise

Exit

3 −State

Enter into

3 −State

at PWM fall

PWM Low and High after

3 −

State to allow Bootstrap

Capacitor Restore Charge

TRUTH TABLE

TPS28225

SLUS710 – MAY 2006

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

SOIC-8

DRB-8

NAME

1

1

UGATE

O

Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET.

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between

2

2

BOOT

I/O

this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper

MOSFET.

The PWM signal is the control input for the driver. The PWM signal can enter three distinct states

3

3

PWM

I

during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further

details. Connect this pin to the PWM output of the controller.

4

4

GND

—

Ground pin. All signals are referenced to this node.

Exposed

Thermal

—

Connect directly to the GND for better thermal performance and EMI

die pad

pad

Lower gate drive sink/source output. Connect to the gate of the low-side power N-Channel

5

5

LGATE

O

MOSFET.

6

6

VDD

I

Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND.

Enable/Power Good input/output pin with 1M

Ω impedance. Connect this pin to HIGH to enable

and LOW to disable the IC. When disabled, the device draws less than 350

µA bias current. If the

7

7

EN/PG

I/O

low.

Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin

8

8

PHASE

I

provides a return path for the upper gate driver.

TIMING DIAGRAM

EN/PG FALLING > 1.0 V

PIN

EN/PG RISING

PWM > 1.5 V AND

PWM SIGNAL SOURCE IMPEDANCE

< 1.7 V

PWM < 1 V

>40 k

LGATE

Low

Low

High

Low

Low

UGATE

Low

Low

Low

High

Low

EN/PG

Low

(1)

To exit the 3-state condition, the PWM signal should go low. One Low PWM input signal followed by one High PWM input signal is

required before re-entering the 3-state condition.

8

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