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MPC9315 Fiches technique(PDF) 5 Page - Motorola, Inc

No de pièce MPC9315
Description  2.5V and 3.3V CMOS PLL Clock Generator and Driver
Download  16 Pages
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Fabricant  MOTOROLA [Motorola, Inc]
Site Internet  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MPC9315 Fiches technique(HTML) 5 Page - Motorola, Inc

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MPC9315
TIMING SOLUTIONS
5
MOTOROLA
DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.7
V
LVCMOS
VOH
Output High Voltage
1.8
V
IOH=-15 mAa
VOL
Output Low Voltage
0.6
V
IOL= 15 mA
ZOUT
Output Impedance
17 - 20
W
IIN
Input Currentb
±200
µA
VIN = VCC or GND
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
a. The MPC9315 is capable of driving 50
Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output.
b. Inputs have pull–up or pull–down resistors affecting the input current.
AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequencyc
÷2 feedback
÷4 feedback
PLL bypass mode
37.50
18.75
0
80
40
TBD
MHz
MHz
MHz
PLL locked
PLL locked
VCCA = GND
fVCO
VCO Lock Range
75c
160c
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2 output
÷4 output
75
37.50
18.75
160
80
50
MHz
MHz
MHz
frefDC
Reference Input Duty Cycle
25
75
%
tr, tf
CLK0, CLK1 Input Rise/Fall Time
1.0
ns
0.7 to 1.7V
t(
∅)
Propagation Delay
CLK0 or CLK1 to FB
(Static Phase Offset)
–150
+150
ps
PLL locked
tSK(
∅)
Output-to-Output Skew
Within one bank
Any output
80
120
ps
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
12
ns
tPZL, LZ
Output Enable Time
12
ns
BW
PLL closed loop bandwidth
÷2 feedback
÷4 feedback
1.0 – 10
0.4 – 3.0
MHz
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
(1
s)
10
22
ps
RMS value
tJIT(PER)
Period Jitter
(1
s)
8.0
15
ps
RMS value
tJIT(
∅)
I/O Phase Jitter
(1
s)
10 – 25b
TBD
ps
RMS value
tLOCK
Maximum PLL Lock Time
1.0
ms
a. AC characteristics apply for parallel output termination of 50
Ω to VTT.
b. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics.
c.
÷1 feedback is not available for VCC = 2.5V operation. Please see next revision of the MPC9315 for the ÷1 feedback option at 2.5V supply.


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