MOTOROLA CMOS LOGIC DATA

MC14536B

10

Figure 10. Time Interval Configuration Using an External Clock, Reset,

and Output Monostable to Achieve a Pulse Output

(Divide–by–4 Configured)

NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset

input low enables the chip’s internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes

Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the

output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock

period) intervals where n = the number of stages selected from the truth table.

PULSE

GEN.

CLOCK

8–BYPASS

A

B

C

D

RESET

SET

CLOCK INH

MONO–IN

CLOCK INH

IN1

VSS

DECODE OUT

OUT 2

OUT 1

8

16

+V

6

9

10

11

12

2

1

7

15

14

3

13

5

4

DECODE OUT

RESET

IN1

POWER UP

VDD

RX

CX

*tw ≈ .00247 • RX • CX0.85

tw in µsec

RX in kΩ

CX in pF

*tw