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CX74038 Datasheet(Fiches technique) 2 Page - Skyworks Solutions Inc.

Numéro de pièce CX74038
Description  2.6 GHz/800 MHz Dual Fractional-N/lnteger-N Frequency Synthesizer
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Fabricant  SKYWORKS [Skyworks Solutions Inc.]
Site Internet  http://www.skyworksinc.com
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DATA SHEET • CX74038
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
2
January 31, 2005 • Skyworks Proprietary and Confidential information • Products and product information are subject to change without notice • 101075I
R1
Divider
R2
Divider
Charge
Pump 1
N1
Divider
N2
Divider
Charge
Pump 2
Serial-to Parallel
Interface
MUX
(LD/TEST)
P/P+1
Prescaler
∆Σ
Modulator
Q/Q+1
Prescaler
P/FD 1
P/FD 2
R1
GND
VDD2_RF
VDD1_RF
GND
GND
CPO_RF
VDD2_IF
VDD1_IF
GND
GND
CPO_IF
SP1
SC1
R2
SP2
SC2
N1
PS
RFIN
FREF
FN
ME
LD_TP
LD
N2
RFINB
IFIN
IFINB
LE
CLK
DAT
C1451
Figure 2. CX74038 Frequency Synthesizer Block Diagram
Technical Description
The CX74038 is a fractional-N frequency synthesizer using a
∆Σ
modulation technique. The fractional-N implementation provides
low in-band noise by having a low division ratio and fast
frequency settling time. In addition, the CX74038 provides
arbitrarily fine frequency resolution with digital words, so that the
frequency synthesizer can be used to compensate for crystal
frequency drift in the RF transceiver.
∆Σ Modulator
Fractional spurs are the primary limitation of conventional
fractional-N synthesizers. The CX74038
∆Σ technique improves
the synthesizer performance by randomizing the spurs using
internal dithering.
Serial Interface
The serial interface is a versatile three-wire interface consisting of
three pins: the serial clock (CLK), serial input (DAT), and Latch
Enable (LE). This interface enables the CX74038 to operate in a
system where one or multiple masters and slaves are present. For
more information, refer to the Synthesizer Register Programming
section of this document.
As shown in Figure 3, LE is set low before the rising edge of the
first clock (CLK) pulse and is held low until after the last (22nd)
clock pulse, at which time LE is set high. The data word is
transferred to the correct device register when LE is high (there
are four internal registers selected by the D1 and D0 bits of the
22-bit data/address word. See Figure 4). If the LE signal does not
go high, the data does not get transferred to the register.
Between each 22-bit data/address word transfer, LE must be
pulsed to make the transfer to the specific device register.
Data/address transfer is MSB first.
LE must not go high when CLK is high; otherwise, the data word
is not transferred to the register. LE must only go high after CLK
has gone low.
After the transfer of the last 22-bit data/address word, the LE
signal can be left in a high state. It does not have to be returned
to a low state unless another data/address word transfer is
required.
It is not necessary to write all four data/address words to the
synthesizer to make a change in programming. For example, if a
change to the Lock Detect (LD) pin operation is desired, only word
00 has to be changed.




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