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74LVCH32374AEC Fiches technique(PDF) 9 Page - NXP Semiconductors |
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74LVCH32374AEC Fiches technique(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 1999 Nov 24 9 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A handbook, full pagewidth MNA500 GND GND th tsu th tsu VM VM VM VI VOH VOL VI nQn output nCP input nDn input Fig.5 Set-up and hold times for inputs (nDn) to inputs (nCP). VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 3-state output enable and disable times. VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VX =VOL + 0.3 V at VCC ≥ 2.7 V; VX =VOL + 0.1 V at VCC < 2.7 V. VY =VOH − 0.3VatVCC ≥ 2.7 V; VY =VOH − 0.1VatVCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. handbook, full pagewidth MNA478 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM |
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