Moteur de recherche de fiches techniques de composants électroniques |
|
74LVC16240ADGG Fiches technique(PDF) 2 Page - NXP Semiconductors |
|
74LVC16240ADGG Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74LVC16240A 16-bit buffer/line driver; inverting (3-State) 2 1997 Jul 29 853-2007 18218 FEATURES • 5 volt tolerant inputs/outputs for interfacing with 5V logic • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels DESCRIPTION The 74LVC16240A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment. The 74LVC16240A is a 16-bit inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74LVC16240A is identical to the 74LVC16244A but has inverting outputs. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1OE 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y1 GND 2Y2 2Y3 3Y0 3Y1 GND 2Y0 3Y2 3Y3 VCC 4Y0 4Y1 4A1 4A0 VCC 3A3 3A2 GND 3A1 3A0 2A3 2A2 GND 2A1 2A0 VCC 1A3 1A2 GND 1A1 1A0 2OE 21 22 23 24 25 26 27 28 GND 4Y2 4Y3 4OE 3OE 4A3 4A2 GND SW00041 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 _C; tr = tf v 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay 1An to 1Yn; 2An to 2Yn CL = 50pF VCC = 3.3V 2.7 ns CI Input capacitance 5.0 pF CPD Power dissipation capacitance per buffer VCC = 3.3V 25 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40 °C to +85°C 74LVC16240A DL VC16240A DL SOT370-1 48-Pin Plastic TSSOP Type II –40 °C to +85°C 74LVC16240A DGG VC16240A DGG SOT362-1 |
Numéro de pièce similaire - 74LVC16240ADGG |
|
Description similaire - 74LVC16240ADGG |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |