Philips Semiconductors

Product specification

74LV74

Dual D-type flip-flop with set and reset;

positive edge-trigger

1998 Apr 20

7

AC WAVEFORMS

output load.

nQ OUTPUT

VM

nD INPUT

nCP INPUT

nQ OUTPUT

GND

GND

SV00335

Figure 1.The clock (nCP) to output (nQ, nQ) propagation

delays, the clock pulse width, the nD to nCP setup times, the

nCP to nD hold times, the output transition times and the

maximum clock pulse frequency

NOTE:

The shaded areas indicate when the input is permitted to change for

predictable output performance.

nCP INPUT

nQ OUTPUT

nQ OUTPUT

GND

GND

GND

SV00336

to nCP removal time

TEST CIRCUIT

PULSE

GENERATOR

D.U.T.

Test Circuit for Outputs

DEFINITIONS

< 2.7V

2.7–3.6V

2.7V

TEST

≥ 4.5 V

50pF

SV00902

Figure 3. Load circuitry for switching times