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UC2864DW Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce UC2864DW
Description  Resonant-Mode Power Supply Controllers
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

UC2864DW Fiches technique(HTML) 7 Page - Texas Instruments

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UC1861-1868
UC2861-2868
UC3861-3868
Minimum oscillator frequency is set by Rmin and Cvco.
The minimum frequency is approximately given by the
equation:
F
RC
MIN
MIN
VCO
43
.
Maximum oscillator frequency is set by Rmin, Range &
Cvco. The maximum frequency is approximately given by
the equation:
F
R
Range
C
MAX
MIN
VCO
33
.
(/ /
)
The Error Amplifier directly controls the oscillator fre-
quency. E/A output low corresponds to minimum fre-
quency and output high corresponds to maximum
frequency. At the end of each oscillator cycle, the RC pin
is discharged to one diode drop above ground. At the be-
ginning of the oscillator cycle, V(RC) is less than Vth1
and so the output of the zero detect comparator is ig-
nored. After V(RC) exceeds Vth1, the one shot pulse will
be terminated as soon as the zero pin falls below 0.5V or
V(RC) exceeds Vth2. The minimum one shot pulse width
is approximately given by the equation:
Tpw(min)
0.3
R
C.
The maximum pulse width is approximately given by:
Tpw(max)
1.2
RC.
APPLICATION INFORMATION
The steering logic is configured on the UC1861,63 to result in
dual non-overlapping square waves at outputs A & B. This is
suited to drive dual switch ZVS systems.
STEERING LOGIC
UDG-92013
The steering logic is configured on the UC1862,64 to result in
inverted pulse trains occurring identically at both output pins.
This is suited to drive single switch ZVS systems. Both outputs
are available to drive the same MOSFET gate. It is advisable to
join the pins with 0.5 ohm resistors.
UDG-92014
The steering logic is configured on the UC1865,67 to result in
alternating pulse trains at outputs A & B. This is suited to drive
dual switch ZCS systems.
UDG-92015
The steering logic is configured on the UC1866,68 to result in
non-inverted pulse trains occurring identically at both output
pins. This is suited to drive single switch ZCS systems. Both
outputs are available to drive the same MOSFET gate. It is ad-
visable to join the pins with 0.5 ohm resistors.
UDG-92016


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