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32170 Datasheet(Fiches technique) 5 Page - Mitsubishi Electric Semiconductor

Numéro de pièce 32170
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Télécharger  49 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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Mitsubishi Microcomputers
5
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Table 3 Outline Performance (1/2)
Functional Block
Features
M32R CPU core
M32R family CPU core, internally configured in 32 bits
Built-in multiplier-accumulator (32
× 16 + 56)
Basic bus cycle : 25 ns (Internal CPU clock frequency at 40 MHz, Internal peripheral
clock frequency at 20 MHz)
Logical address space : 4G bytes, linear
General-purpose register : 32-bit register
× 16, Control register: 32-bit register × 5
accumulator : 56 bits
External data bus
16 bits data bus
Instruction set
16-bit/32-bit instruction formats
83 instructions/ 9 addressing modes
Internal flash memory
M32170F6 : 768K bytes
M32170F4, M32174F4 : 512K bytes
M32170F3, M32174F3 : 384K bytes
Rewrite durability : 100 times
Internal RAM
M32170F6, M32174F4, M32174F3 : 40K bytes
M32170F4, M32170F3 : 32K bytes
DMAC
10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral
I/O and internal RAM, and between internal RAMs)
Channels can be cascaded and can operate in combination with internal peripheral I/O
Multijunction timer
64 channels of multijunction timers.
• 16-bit output-related timers
× 35 channels (single-shot, delayed single-shot, PWM, single-shot PWM)
• 16-bit input/output-related timers
× 10 channels (event count mode, single-shot, PWM, measurement)
• 16-bit input-related timers
× 11 channels (measurement, event count mode, multiply-by-4 count 3 channels)
• 32-bit input-related timers
× 8 channels (measurement)
Flexible timer configuration is possible through interconnection of channels using the event bus.
A-D converter
2 independent 10-bit multifunction A-D converters
• Input 16 channels
× 2
• Scan-based conversion can be switched with 4, 8, and 16
• Capable of interrupt conversion during scan
• 8-bit/10-bit readout function available
Serial I/O
6 channels (The serial I/Os can be set for synchronous serial I/O or UART.
SIO2,3 are UART mode only)
Real-time debugger (RTD)
1-channels dedicated clock-synchronized serial
The entire internal RAM can be read or rewritten from the outside without CPU intervention.
Interrupt controller
Controls interrupts from internal peripheral I/Os
(Priority can be set to one of 8 levels including interrupt disabled)
Wait controller
Controls wait when accessing external extended area
(1 to 4 wait cycles inserted + prolonged by external WAIT signal input)
CAN
16-channels message slots
JTAG
Boundary-Scan function




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Datasheet Download



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