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AD5628BRUZ-2 Fiches technique(PDF) 10 Page - Analog Devices |
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AD5628BRUZ-2 Fiches technique(HTML) 10 Page - Analog Devices |
10 / 24 page AD5628/AD5648/AD5668 Preliminary Technical Data Rev.PrA | Page 10 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SYNC VOUTA 1 2 14 13 5 6 7 10 9 8 3 4 12 11 TOP VIEW (Not to Scale) AD5628 AD5648 AD5668 DIN GND VDD SCLK VOUTB VOUTD VOUTC VOUTE VOUTF VOUTG VOUTH VREF LDAC SYNC VOUTA 1 2 16 15 5 6 7 12 11 10 3 4 14 13 8 9 TOP VIEW (Not to Scale) AD5628 AD5648 AD5668 DIN GND VDD SCLK VOUTB VOUTD VOUTC VOUTE VOUTF VOUTG VOUTH CLR VREF Figure 3. 14-Lead TSSOP (RU-14) Figure 4. 16-Lead TSSOP (RU-16) Table 2. Pin Function Descriptions Pin No. Mnemonic Function 1 /LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 2 /SYNC Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 13 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 5 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 12 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 8 VREF Reference Input/Output Pin 9 /CLR Active Low Control Input that Loads Software selectable code – Zero, midscale, fullscale - to All Input and DAC Registers. Therefore, the outputs also go to selected code. Default clears the output to 0V. 6 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. 11 VOUTF Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. 7 VOUTG Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. 10 VOUTH Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. 14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. |
Numéro de pièce similaire - AD5628BRUZ-2 |
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Description similaire - AD5628BRUZ-2 |
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