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74LV126 Fiches technique(PDF) 6 Page - NXP Semiconductors |
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74LV126 Fiches technique(HTML) 6 Page - NXP Semiconductors |
6 / 12 page Philips Semiconductors Product specification 74LV126 Quad buffer/line driver (3-State) 1998 Apr 28 6 AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6 V; VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V; VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC ≥ 2.7 V and ≤ 3.6 V; VX = VOL + 0.1 × VCC at VCC < 2.7 V and ≥ 4.5 V. VY = VOH – 0.3 V at VCC ≥ 2.7 V and ≤ 3.6 V; VY = VOH – 0.1 × VCC at VCC < 2.7 V and ≥ 4.5 V. SV00487 nA INPUT nY OUTPUT GND V I V OL V OH t PHL t PLH V M V M Figure 1. Input (nA, nB) to output (nY) propagation delays SV00488 outputs disabled outputs enabled outputs enabled t PHZ t PZL t PLZ V X V Y V M V M V M nOE INPUT VI GND V CC V OL VOH GND OUTPUT HIGH-to-OFF OFF-to-HIGH OUTPUT LOW-to-OFF OFF-to-LOW t PZH Figure 2. 3-state enable and disable times. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR RT VI D.U.T. VO CL RL = 1k VCC Test Circuit for Outputs DEFINITIONS VCC VI < 2.7V VCC TEST tPLH/tPHL RT = Termination resistance should be equal to ZOUT of pulse generators. 2.7V 2.7–3.6V w 4.5V VCC 50 pF SV00896 S1 tPLZ/tPZL tPHZ/tPZH Open 2 * VCC GND RL = 1k Open 2 * VCC GND RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. Figure 3. Load circuitry for switching times. |
Numéro de pièce similaire - 74LV126 |
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Description similaire - 74LV126 |
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