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74HC4094D Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74HC4094D Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 10 page December 1990 10 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 AC WAVEFORMS Fig.7 Waveforms showing the clock (CP) to output (QPn,QS1,QS2) propagation delays, the clock pulse width and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the strobe (STR) to output (QPn) propagation delays and the strobe pulse width and the clock set-up and hold times for the strobe input. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times for input OE. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.10 Waveforms showing the data set-up and hold times for the data input (D). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
Numéro de pièce similaire - 74HC4094D |
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Description similaire - 74HC4094D |
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