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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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74HCT40104 Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74HCT40104 Fiches technique(HTML) 2 Page - NXP Semiconductors |
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2 / 8 page  December 1990 2 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state 74HC/HCT40104 FEATURES • Synchronous parallel or serial operating • 3-state outputs • Output capability: bus driver • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40104 are high-speed Si-gate CMOS devices and are pin compatible with the “40104” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40104 are universal shift registers featuring parallel inputs, parallel outputs, shift-right and shift-left serial inputs and 3-state outputs allowing the devices to be used in bus-organized systems. In the parallel-load mode (S0 and S1 are HIGH), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge with serial data entered at the shift-right (DSR) and shift-left (DSL) serial inputs, respectively. Clearing the register is accomplished by setting both mode controls (S0 and S1) LOW and clocking the register. When the output enable input (OE) is LOW, all outputs assume the high-impedance OFF-state (Z). APPLICATIONS • Arithmetic unit bus registers • Serial/parallel conversion • General-purpose register for bus organized systems • General-purpose registers QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay CP to Qn CL = 15 pF; VCC = 5 V 13 15 ns fmax maximum clock frequency 62 57 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 75 75 pF |
Numéro de pièce similaire - 74HCT40104 |
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Description similaire - 74HCT40104 |
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