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74HCT356 Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74HCT356 Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 13 page December 1990 2 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state 74HC/HCT356 FEATURES • Non-transparent data latches • Transparent address latch • Easily expanding • Complementary outputs • Output capability: bus driver • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT356 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT356 data selectors/multiplexers contain full on-chip binary decoding, to select one-of-eight data sources. The data select address is stored in transparent latches that are enabled by a LOW on the latch enable input LE. Data on the 8 input lines (D0 to D7) is clocked into a edge-triggered data register by a LOW-to-HIGH transition of the clock (CP). When the output enable input OE1 = HIGH, OE2 = HIGH or OE3 = LOW, the outputs go to the high impedance OFF-state. Operation of these output enable inputs does not affect the state of the latches and register. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay CL = 15 pF; VCC =5 V Sn, LE to Y, Y24 25 ns CP to Y, Y20 22 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 123 125 pF |
Numéro de pièce similaire - 74HCT356 |
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Description similaire - 74HCT356 |
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