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74HCT194 Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74HCT194 Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 10 page December 1990 10 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74HC/HCT194 AC WAVEFORMS Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the set-up and hold times from the data inputs (Dn, DSR and DSL) to the clock (CP). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.10 Waveforms showing the set-up and hold times from the mode control inputs (Sn) to the clock input (CP). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
Numéro de pièce similaire - 74HCT194 |
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Description similaire - 74HCT194 |
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