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74HCT109DB Fiches technique(PDF) 6 Page - NXP Semiconductors |
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74HCT109DB Fiches technique(HTML) 6 Page - NXP Semiconductors |
6 / 9 page 1997 Nov 25 6 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nCP to nQ, nQ 20 35 44 53 ns 4.5 Fig.6 tPLH propagation delay nSD to nQ 13 26 33 39 ns 4.5 Fig.7 tPHL propagation delay nSD to nQ 19 35 44 53 ns 4.5 Fig.7 tPHL propagation delay nRD to nQ 19 35 44 53 ns 4.5 Fig.7 tPLH propagation delay nRD to nQ 16 32 40 48 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 18 9 23 27 ns 4.5 Fig.6 tW set or reset pulse width HIGH or LOW 16 8 20 24 ns 4.5 Fig.7 trem removal time nSD, nRD to nCP 16 8 20 24 ns 4.5 Fig.7 tsu set-up time nJ, nK to nCP 18 8 23 27 ns 4.5 Fig.6 th hold time nJ, nK to nCP 3 −3 3 3 ns 4.5 Fig.6 fmax maximum clock pulse frequency 27 55 22 18 MHz 4.5 Fig.6 |
Numéro de pièce similaire - 74HCT109DB |
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Description similaire - 74HCT109DB |
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